IEEE - Institute of Electrical and Electronics Engineers, Inc. - 2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

2019 IEEE International Solid- State Circuits Conference - (ISSCC)

Author(s): Takashi Takemoto ; Masato Hayashi ; Chihiro Yoshimura ; Masanao Yamaoka
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 2019
Conference Location: San Francisco, CA, USA, USA
Conference Date: 17 February 2019
Page(s): 52 - 54
ISBN (Electronic): 978-1-5386-8531-0
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2019.8662517
Regular:

The last decade has seen impressive progress in the development of a new computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for... View More

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