IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution

Author(s): Kwangsoo Han ; Andrew B. Kahng ; Jiajia Li
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1
ISSN (Electronic): 1937-4151
ISSN (Paper): 0278-0070
DOI: 10.1109/TCAD.2018.2889756
Regular:

Clock power, skew and maximum latency are three key metrics for clock distribution in low-power and high-performance designs. An H-tree offers minimum clock skew and good robustness against... View More

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