SMTA - Chip Board Interaction Analysis of 22-NM Fully Depeleted Silicon on Insulator (FD-SOI) Technology in Wafer Level Packaging (WLP)

2018 International Wafer Level Packaging Conference (IWLPC)

Author(s): Jae Kyu Cho ; Jens Paul ; Simone Capecchi ; Dirk Breuer ; Frank Kuechenmeister ; Doug Scott ; JongJin Choi ; Wonjoon Kang
Publisher: SMTA
Publication Date: 1 October 2018
Conference Location: San Jose, CA, USA, USA
Conference Date: 23 October 2018
Page(s): 1 - 6
ISBN (Electronic): 978-1-9445-4306-8
DOI: 10.23919/IWLPC.2018.8573290

Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The... View More