IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of a Low Noise Clock Generator Based on TSMC65nm Process

2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Author(s): Ke-wei Xin ; Fang-xu Lv ; Jian-ye Wang ; Lei Bao ; Meng-yang Cui
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2018
Conference Location: Qingdao, China, China
Conference Date: 31 October 2018
Page(s): 1 - 3
ISBN (CD): 978-1-5386-4439-3
ISBN (Electronic): 978-1-5386-4441-6
ISBN (Paper): 978-1-5386-4440-9
DOI: 10.1109/ICSICT.2018.8564980
Regular:

This paper designed a low noise 14 GHz phase-locked loop (PLL) for high-speed serial interface. We use a differential structure with a feedback charge pump to reduce the system's common-mode noise... View More

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