IEEE - Institute of Electrical and Electronics Engineers, Inc. - High SFDR Pipeline ROM-less DDFS Design on FPGA Platform Using Parabolic Equations

2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

Author(s): Chua-Chin Wang ; Hsiang-Yu Shih ; Wei Wang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2018
Conference Location: Qingdao, China, China
Conference Date: 31 October 2018
Page(s): 1 - 4
ISBN (CD): 978-1-5386-4439-3
ISBN (Electronic): 978-1-5386-4441-6
ISBN (Paper): 978-1-5386-4440-9
DOI: 10.1109/ICSICT.2018.8564929
Regular:

A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster... View More

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