IEEE - Institute of Electrical and Electronics Engineers, Inc. - Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

2018 IEEE 27th Asian Test Symposium (ATS)

Author(s): Satoshi Hirai ; Hiroyuki Yotsuyanagi ; Masaki Hashizume
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2018
Conference Location: Hefei, China, China
Conference Date: 15 October 2018
Page(s): 7 - 12
ISBN (Electronic): 978-1-5386-9466-4
ISSN (Electronic): 2377-5386
DOI: 10.1109/ATS.2018.00013
Regular:

A boundary scan design with embedded time-to-digital converter (TDCBS) has been proposed for testing small delay faults. In this paper, the TDCBS is applied for testing TSVs in 3D IC. To reduce... View More

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