IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE

2018 IEEE 27th Asian Test Symposium (ATS)

Author(s): Zhengfeng Huang ; Yangyang Zhang ; Zian Su ; Huaguo Liang ; Huijie Yao ; Tianming Ni
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2018
Conference Location: Hefei, China, China
Conference Date: 15 October 2018
Page(s): 121 - 126
ISBN (Electronic): 978-1-5386-9466-4
ISSN (Electronic): 2377-5386
DOI: 10.1109/ATS.2018.00033
Regular:

With technology scaling, nanoscale CMOS becomes more sensitive to Multiple Node Upsets (MNUs). This paper presents a Multiple Node Upsets Tolerant Hardened Latch based on hybrid Double Modular... View More

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