IEEE - Institute of Electrical and Electronics Engineers, Inc. - 1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time

Author(s): Avinash Lahgere ; Mamidala Jagadesh Kumar
Sponsor(s): IEEE Nanotechnology Council
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2018
Volume: 17
Page(s): 543 - 551
ISSN (Electronic): 1941-0085
ISSN (Paper): 1536-125X
DOI: 10.1109/TNANO.2018.2825394
Regular:

In this paper, a single transistor (1-T) capacitorless DRAM using laterally bandgap engineered Si-Si:C heterostructure bipolar I-MOS is investigated using 2-D calibrated simulations. The proposed... View More

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