IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement

2018 IEEE Symposium on VLSI Circuits

Author(s): Hossein Valavi ; Peter J. Ramadge ; Eric Nestler ; Naveen Verma
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2018
Conference Location: Honolulu, HI, USA
Conference Date: 18 June 2018
Page(s): 141 - 142
ISBN (Electronic): 978-1-5386-4214-6
DOI: 10.1109/VLSIC.2018.8502421
Regular:

We present a 65nm CMOS mixed-signal accelerator for first and hidden layers of binarized CNNs. Hidden layers support up to 512, 3 ×3 ×512 binary - input filters, and first layers support up to 64,... View More

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