IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET

2018 IEEE Symposium on VLSI Circuits

Author(s): James Hudner ; Declan Carey ; Ronan Casey ; Kay Hearne ; Pedro Wilson de Abreu Farias Neto ; Ilias Chlis ; Marc Erett ; Chi Fung Poon ; Asma Laraba ; Hongtao Zhang ; Sai Lalith Chaitanya Ambatipudi ; David Mahashin ; Parag Upadhyaya ; Yohan Frans ; Ken Chang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2018
Conference Location: Honolulu, HI, USA
Conference Date: 18 June 2018
Page(s): 47 - 48
ISBN (Electronic): 978-1-5386-4214-6
DOI: 10.1109/VLSIC.2018.8502436
Regular:

A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance buffer, and a 56GSa/s 64-way... View More

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