IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing

2018 IEEE Symposium on VLSI Circuits

Author(s): L. Millet ; S. Chevobbe ; C. Andriamisaina ; E. Beigne ; F. Guellec ; T. Dombek ; L. Benaissa ; E. Deschaseaux ; M. Duranton ; K. Benchehida ; M. Darouich ; M. Lepecq
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2018
Conference Location: Honolulu, HI, USA
Conference Date: 18 June 2018
Page(s): 245 - 246
ISBN (Electronic): 978-1-5386-4214-6
DOI: 10.1109/VLSIC.2018.8502290
Regular:

This paper presents a 2-layer 3D stacked Back Side Illuminated vision chip performing high speed programmable parallel computing by exploiting in-focal-plane pixel readout circuits. The proposed... View More

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