IEEE - Institute of Electrical and Electronics Engineers, Inc. - Implementation of a Two-Processor CPU for a Programmable Logic Controller Designed on FPGA Chip

2018 International Conference on Signals and Electronic Systems (ICSES)

Author(s): Miroslaw Chmiel ; Jan Mocha ; Artur Lech
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2018
Conference Location: Krako┬┤w, Poland
Conference Date: 10 September 2018
Page(s): 13 - 18
ISBN (Electronic): 978-1-5386-6768-2
ISBN (USB): 978-1-5386-6767-5
ISSN (Electronic): 2474-2465
DOI: 10.1109/ICSES.2018.8507283
Regular:

The study presents details related to the structure of a two-processor CPU designed for a PLC. The CPU is made up of a 1-bit processor combined with a 32-bit processor and is capable of executing... View More

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