IEEE - Institute of Electrical and Electronics Engineers, Inc. - Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Author(s): John H. Lau ; Ming Li ; Margie Li Qingqian ; Tony Chen ; Iris Xu ; Qing Xiang Yong ; Zhong Cheng ; Nelson Fan ; Eric Kuah ; Zhang Li ; Kim Hwee Tan ; Yiu-Ming Cheung ; Eric Ng ; Penny Lo ; Wu Kai ; Ji Hao ; Koh Sau Wee ; Jiang Ran ; Cao Xi ; Rozalia Beica ; Sze Pei Lim ; N. C. Lee ; Cheng-Ta Ko ; Henry Yang ; Yu-Hua Chen ; Mian Tao ; Jeffery Lo ; Ricky S. W. Lee
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2018
Volume: 8
Page(s): 1,544 - 1,560
ISSN (Electronic): 2156-3985
ISSN (Paper): 2156-3950
DOI: 10.1109/TCPMT.2018.2848649
Regular:

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in... View More

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