IEEE - Institute of Electrical and Electronics Engineers, Inc. - A New FPGA-Based Segmented Delay-Line DPWM With Compensation for Critical Path Delays

Author(s): Xin Cheng ; Ruifeng Song ; Guangjun Xie ; Yu Zhang ; Zhang Zhang
Sponsor(s): IEEE Power Electronics Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2018
Volume: 33
Page(s): 10,794 - 10,802
ISSN (Electronic): 1941-0107
ISSN (Paper): 0885-8993
DOI: 10.1109/TPEL.2017.2763750
Regular:

The duty cycle in digital pulse width modulation (DPWM) whose time resolution is as high as hundreds of picosecond will be increased since the propagation delays of internal logics and... View More

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