IEEE - Institute of Electrical and Electronics Engineers, Inc. - Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Author(s): Joshua Liang ; Ali Sheikholeslami ; Hirotaka Tamura ; Yuuki Ogata ; Hisakatsu Yamaguchi
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2018
Volume: 53
Page(s): 2,696 - 2,708
ISSN (Electronic): 1558-173X
ISSN (Paper): 0018-9200
DOI: 10.1109/JSSC.2018.2839038
Regular:

A loop gain adaptation technique is proposed, which optimizes the jitter tolerance (JTOL) of a 28 Gb/s phase interpolator (PI)-based clock and data recovery (CDR) circuit implemented in 28 nm... View More

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