IEEE - Institute of Electrical and Electronics Engineers, Inc. - Circuit and Methodology for Testing Small Delay Faults in the Clock Network

Author(s): Shao-Fu Yang ; Zhi-Yuan Wen ; Shi-Yu Huang ; Kun-Han Tsai ; Wu-Tung Cheng
Sponsor(s): IEEE Council on Electronic Design Automation
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2018
Volume: 37
Page(s): 2,087 - 2,097
ISSN (Electronic): 1937-4151
ISSN (Paper): 0278-0070
DOI: 10.1109/TCAD.2018.2789779
Regular:

A clock network is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, small defects in a clock tree network could lead... View More

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