IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS

Author(s): Srinivasan Gopal ; Pawan Agarwal ; Joe Baylon ; Luke Renaud ; Sheikh Nijam Ali ; Partha Pratim Pande ; Deukhyoun Heo
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2018
Volume: 8
Page(s): 506 - 518
ISSN (Electronic): 2156-3365
ISSN (Paper): 2156-3357
DOI: 10.1109/JETCAS.2018.2852624
Regular:

Large-scale parallel implementation of matrix multiply and accumulate (MAC) core poses significant energy and area constraints in analog voltage domain under reduced supply voltage. A spatial... View More

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