IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Author(s): Kwanseo Park ; Woorham Bae ; Jinhyung Lee ; Jeongho Hwang ; Deog-Kyoon Jeong
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1 - 12
ISSN (Electronic): 1558-173X
ISSN (Paper): 0018-9200
DOI: 10.1109/JSSC.2018.2859947
Regular:

A single-loop referenceless clock and data recovery (CDR) with a compact frequency acquisition scheme is presented. A bang-bang phase-frequency detector (BBPFD) is proposed that tracks the... View More

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