IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

Author(s): Yan Zhu ; Chi-Hang Chan ; Zi-Hao Zheng ; Cheng Li ; Jian-Yu Zhong ; Rui P. Martins
Sponsor(s): IEEE Circuits and Systems Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Volume: PP
Page(s): 1 - 11
ISSN (Electronic): 1558-0806
ISSN (Paper): 1549-8328
DOI: 10.1109/TCSI.2018.2859027
Regular:

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical... View More

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