IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash

Author(s): Shou-Han Chen ; Yuan-Hao Chang ; Yu-Pei Liang ; Hsin-Wen Wei ; Wei-Kuan Shih
Sponsor(s): IEEE Comput. Soc. Tech. Committee on Distributed Process
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2018
Volume: 67
Page(s): 1,246 - 1,258
ISSN (CD): 2326-3814
ISSN (Electronic): 1557-9956
ISSN (Paper): 0018-9340
DOI: 10.1109/TC.2018.2818118
Regular:

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques,... View More

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