IEEE - Institute of Electrical and Electronics Engineers, Inc. - Circuit-Level Layout-Aware Modeling of Single-Event Effects in 65-nm CMOS ICs

Author(s): Anton O. Balbekov ; Maxim S. Gorbunov ; Gennady I. Zebrev
Sponsor(s): IEEE Nuclear and Plasma Sciences Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2018
Volume: 65
Page(s): 1,914 - 1,919
ISSN (Electronic): 1558-1578
ISSN (Paper): 0018-9499
DOI: 10.1109/TNS.2018.2802205
Regular:

We present a convenient layout-aware circuit-level modeling technique based on two modeling approaches: single spot and distributed circuit representing the diffusion- and circuit-driven charge... View More

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