IEEE - Institute of Electrical and Electronics Engineers, Inc. - On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology

2007 10th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Author(s): D. Roberts ; Nam Sung Kim ; T. Mudge
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 August 2007
Conference Location: Lubeck, Germany
Conference Date: 29 August 2007
Page(s): 570 - 578
ISBN (Paper): 978-0-7695-2978-3
DOI: 10.1109/DSD.2007.4341526
Regular:

In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of current... View More

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