IEEE - Institute of Electrical and Electronics Engineers, Inc. - Timing Error Calibration in Time-Interleaved ADC by Sampling Clock Phase Adjustment

2007 IEEE Instrumentation and Measurement Technology Conference

Author(s): Zheng Liu ; K. Honda ; M. Furuta ; S. Kawahito
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: Warsaw, Poland
Conference Date: 1 May 2007
Page(s): 1 - 4
ISBN (CD): 1-4244-1080-0
ISBN (Paper): 1-4244-0588-2
ISSN (Paper): 1091-5281
DOI: 10.1109/IMTC.2007.379401
Regular:

Timing error between sampling and holding (SZH) channels for Time-interleaved analog-to-digital converts (TiADCs) is caused by clock skew and RC (sampling resistance and capacitance) mismatch.... View More

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