IEEE - Institute of Electrical and Electronics Engineers, Inc. - Low-power design technique for flash A/D converters based on reduction of the number of comparators

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): T. Sato ; S. Takagi ; N. Fujii
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 3,606 - 3,609
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.378533
Regular:

This paper proposes a low-power, small chip area design technique for flash analog-to-digital converters (A/D converters). The proposed technique reduces power consumption of flash A/D converters... View More

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