IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): M. Alioto ; G. Palumbo
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 2,998 - 3,001
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.377977
Regular:

In this paper, the mixed-topology Full Adder chains proposed in [1] are extensively analyzed versus technology. Analysis aims at exploring the power-delay design space in mixed-topology full adder... View More

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