IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): Yanfeng Wang ; Qiang Zhou ; Xianlong Hong ; Yici Cai
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 2,040 - 2,043
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.378498
Regular:

Minimization of clock network is traditionally achieved by clock routing, which may be helpless for a poor placement result. In this paper, a novel dynamic clock-tree building technique integrated... View More

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