IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): R. Hentschke ; R. Reis
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 2,036 - 2,039
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.378497
Regular:

This paper studies the 3D-via placement problem for 3D circuits. We model the problem in such a way that 3D-vias are assigned to layers between the circuit tiers. The placement problem consists of... View More

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