IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoC

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): H. Tohya ; N. Toya
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 889 - 892
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.378049
Regular:

The novel design methodology of the on-chip power distribution network (PDN) is presented in this paper. The low-impedance lossy line (LILL) technology is used for the on-chip PDN instead of the... View More

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