IEEE - Institute of Electrical and Electronics Engineers, Inc. - GALS Based Shared Test Architecture for Embedded Memories

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): P. Dubey ; A. Garg ; S.K. Bhaskarani
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: New Orleans, LA, USA
Conference Date: 27 May 2007
Page(s): 157 - 160
ISBN (CD): 1-4244-0921-7
ISBN (Paper): 1-4244-0920-9
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2007.378245
Regular:

Increasing memory content on SoCs, along with the shrinking technology node (resulting into newer kinds of defects), multiple clocks, and voltage domains necessitate a shared built in self test... View More

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