IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient Evaluation of Substrate Warpage by Finite Element Method and Factorial Design Analysis

2007 Electronic Components and Technology Conference

Author(s): Tsrong-Yi Wen ; Shih-Chang Ku
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: Reno, NV, USA
Conference Date: 29 May 2007
Page(s): 1,754 - 1,759
ISBN (CD): 1-4244-0985-3
ISBN (Paper): 1-4244-0984-5
ISSN (Paper): 0569-5503
DOI: 10.1109/ECTC.2007.374033
Regular:

Warpage of flip chip package is mainly dominated by the substrate stack-up. Mismatch by coefficient of thermal expansion (CTE) and Young's modulus (E) in package materials should be responsible to... View More

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