IEEE - Institute of Electrical and Electronics Engineers, Inc. - Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

2007 Electronic Components and Technology Conference

Author(s): D. Henry ; X. Baillin ; V. Lapras ; M.H. Vaudaine ; J.M. Quemper ; N. Sillon ; B. Dunne ; C. Hernandez ; E. Vigier-Blanc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: Reno, NV, USA
Conference Date: 29 May 2007
Page(s): 830 - 835
ISBN (CD): 1-4244-0985-3
ISBN (Paper): 1-4244-0984-5
ISSN (Paper): 0569-5503
DOI: 10.1109/ECTC.2007.373894
Regular:

In this paper a new 'via-first' technology which is compatible with CMOS high temperature steps will be presented. This technology is based on filling high aspect ratio trenches with doped... View More

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