IEEE - Institute of Electrical and Electronics Engineers, Inc. - Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures

2007 International Symposium on Networks-on-Chip

Author(s): I. Miro Panades ; A. Greiner
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2007
Conference Location: Princeton, NJ, USA
Conference Date: 7 May 2007
Page(s): 83 - 94
ISBN (Paper): 0-7695-2773-6
DOI: 10.1109/NOCS.2007.14
Regular:

The distribution of a synchronous clock in system-on-chip (SoC) has become a problem, because of wire length and process variation. Novel approaches such as the globally asynchronous, locally... View More

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