IEEE - Institute of Electrical and Electronics Engineers, Inc. - High Level RTOS Scheduler Modeling for a Fast Design Validation

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). Emerging VLSI Technologies and Architectures

Author(s): F. Hessel ; C. Marcon ; T. Santos
Sponsor(s): IEEE Comput. Soc. Tech. Comm. VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Porto Alegre, Brazil
Conference Date: 9 March 2007
Page(s): 461 - 466
ISBN (Paper): 0-7695-2896-1
DOI: 10.1109/ISVLSI.2007.49
Regular:

The use of higher level specification models will open new sceneries for optimization and architecture exploration like CPU/RTOS tradeoffs. Scheduling decision for realtime embedded applications... View More

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