IEEE - Institute of Electrical and Electronics Engineers, Inc. - Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). Emerging VLSI Technologies and Architectures

Author(s): B. Zatt ; A. Azevedo ; L. Agostini ; A. Susin ; S. Bampi
Sponsor(s): IEEE Comput. Soc. Tech. Comm. VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Porto Alegre, Brazil
Conference Date: 9 March 2007
Page(s): 445 - 446
ISBN (Paper): 0-7695-2896-1
DOI: 10.1109/ISVLSI.2007.64
Regular:

This paper presents a motion compensation memory hierarchy for an H.264/AVC decoder with support to bi-predictive frames. The designed memory hierarchy reduces the memory bandwidth through the use... View More

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