IEEE - Institute of Electrical and Electronics Engineers, Inc. - High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). Emerging VLSI Technologies and Architectures

Author(s): Saihua Lin ; Huazhong Yang ; Rong Luo
Sponsor(s): IEEE Comput. Soc. Tech. Comm. VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Porto Alegre, Brazil
Conference Date: 9 March 2007
Page(s): 273 - 278
ISBN (Paper): 0-7695-2896-1
DOI: 10.1109/ISVLSI.2007.50
Regular:

In this paper, a novel soft-error-tolerant latch and a novel soft-error-tolerant flip-flop are presented for multiple VDD circuit design. By utilizing local redundancy, the latch and the flip-flop... View More

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