IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design and Analysis of Low Power Dynamic Bus Based on RLC simulation

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). Emerging VLSI Technologies and Architectures

Author(s): Shanq-Jang Ruan ; Shang-Fang Tsai ; Yu-Ting Pai
Sponsor(s): IEEE Comput. Soc. Tech. Comm. VLSI
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Porto Alegre, Brazil
Conference Date: 9 March 2007
Page(s): 113 - 118
ISBN (Paper): 0-7695-2896-1
DOI: 10.1109/ISVLSI.2007.36
Regular:

In this paper, we propose a low power dynamic bus encoding scheme which simultaneously reduces the capacitive and inductive effects by the measurement of real RLC model. It should be noted that... View More

Advertisement