IEEE - Institute of Electrical and Electronics Engineers, Inc. - Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions

2007 IEEE International Parallel and Distributed Processing Symposium

Author(s): C.J. Ihrig ; J. Stander ; A.K. Jones
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Rome, Italy
Conference Date: 26 March 2007
Page(s): 1 - 8
ISBN (CD): 1-4244-0910-1
ISBN (Paper): 1-4244-0909-8
DOI: 10.1109/IPDPS.2007.370468
Regular:

Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, another technique to... View More

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