IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs

2007 IEEE International Parallel and Distributed Processing Symposium

Author(s): M. Boden ; T. Fiebig ; T. Meissner ; S. Rulke ; J. Becker
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Rome, Italy
Conference Date: 26 March 2007
Page(s): 1 - 8
ISBN (CD): 1-4244-0910-1
ISBN (Paper): 1-4244-0909-8
DOI: 10.1109/IPDPS.2007.370390
Regular:

This paper presents a novel high-level synthesis (HLS) and optimization approach targeting FPGA architectures that are reconfigurable at run-time. To model a reconfigurable system on a high level... View More

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