IEEE - Institute of Electrical and Electronics Engineers, Inc. - Towards Optimal Multi-level Tiling for Stencil Computations

2007 IEEE International Parallel and Distributed Processing Symposium

Author(s): Lakshminarayanan Renganarayana ; Manjukumar Harthikote-Matha ; Rinku Dewri ; Sanjay Rajopadhye
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: Rome, Italy
Conference Date: 26 March 2007
Page(s): 1 - 10
ISBN (CD): 1-4244-0910-1
ISBN (Paper): 1-4244-0909-8
DOI: 10.1109/IPDPS.2007.370291
Regular:

Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many tiling and... View More

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