IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

2007 Asia and South Pacific Design Automation Conference

Author(s): Cheoljoo Jeong ; S.M. Nowick
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2007
Conference Location: Yokohama, Japan
Conference Date: 23 January 2007
Page(s): 622 - 627
ISBN (CD): 1-4244-0630-7
ISBN (Paper): 1-4244-0629-3
DOI: 10.1109/ASPDAC.2007.358055
Regular:

As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is... View More

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