IEEE - Institute of Electrical and Electronics Engineers, Inc. - Formal Validation of Hierarchical State Machines against Expectations

2007 18th Australian Software Engineering Conference

Author(s): I. Toyn ; A. Galloway
Sponsor(s): Data Processors Infosys Australia
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2007
Conference Location: Melbourne, Vic., Australia
Conference Date: 10 April 2007
Page(s): 181 - 190
ISBN (Paper): 0-7695-2778-7
ISSN (Paper): 1530-0803
DOI: 10.1109/ASWEC.2007.23
Regular:

This paper explains some analyses that can be performed on a hierarchical finite state machine to validate that it performs as intended. Such a hierarchical state machine has transitions between... View More

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