IEEE - Institute of Electrical and Electronics Engineers, Inc. - Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis

2007 IEEE International Symposium on Quality of Electronic Design

Author(s): Joon-Sung Yang ; A. Rajaram ; N. Shi ; Jian Chen ; D.Z. Pan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: San Jose, CA, USA
Conference Date: 26 March 2007
Page(s): 398 - 403
ISBN (Paper): 0-7695-2795-7
DOI: 10.1109/ISQED.2007.142
Regular:

Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, power-ground noise... View More

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