IEEE - Institute of Electrical and Electronics Engineers, Inc. - Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

2007 IEEE International Symposium on Quality of Electronic Design

Author(s): M.Q. Do ; M. Drazdziulis ; P. Larsson-Edefors ; L. Bengtsson
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: San Jose, CA, USA
Conference Date: 26 March 2007
Page(s): 185 - 191
ISBN (Paper): 0-7695-2795-7
DOI: 10.1109/ISQED.2007.97
Regular:

We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic... View More

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