IEEE - Institute of Electrical and Electronics Engineers, Inc. - Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

2007 IEEE International Symposium on Quality of Electronic Design

Author(s): S.A. Tawfik ; V. Kursun
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 March 2007
Conference Location: San Jose, CA, USA
Conference Date: 26 March 2007
Page(s): 73 - 78
ISBN (Paper): 0-7695-2795-7
ISSN (Electronic): 1948-3295
ISSN (Paper): 1948-3287
DOI: 10.1109/ISQED.2007.65
Regular:

A methodology based on supply voltage scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock... View More

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