IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Memory-Level Parallelism Aware Fetch Policy for SMT Processors

2007 IEEE 13th International Symposium on High Performance Computer Architecture

Author(s): Stijn Everman ; Lieven Eeckhout
Sponsor(s): IEEE Comput. Soc. Tech. Comm. on Comput. Archit
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 2007
Conference Location: Scottsdale, AZ, USA
Conference Date: 10 February 2007
Page(s): 240 - 249
ISBN (CD): 1-4244-0805-9
ISBN (Paper): 1-4244-0804-0
ISSN (Electronic): 2378-203X
ISSN (Paper): 1530-0897
DOI: 10.1109/HPCA.2007.346201
Regular:

A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-latency load aware... View More

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