IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Placement Methodology for Robust Clocking

2007 20th International Conference on VLSI Design

Author(s): G. Venkataraman ; Jiang Hu
Sponsor(s): VLSI Soc. of India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2007
Conference Location: Bangalore, India
Conference Date: 6 January 2007
Page(s): 881 - 886
ISBN (Paper): 0-7695-2762-0
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2007.20
Regular:

As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in performance... View More

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