IEEE - Institute of Electrical and Electronics Engineers, Inc. - Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

2007 20th International Conference on VLSI Design

Author(s): Gefu Xu ; A.D. Singh
Sponsor(s): VLSI Soc. of India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2007
Conference Location: Bangalore, India
Conference Date: 6 January 2007
Page(s): 763 - 768
ISBN (Paper): 0-7695-2762-0
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2007.61
Regular:

Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with... View More

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