IEEE - Institute of Electrical and Electronics Engineers, Inc. - Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver

2007 20th International Conference on VLSI Design

Author(s): R. Bagheri ; A. Mirzaei ; S. Chehrazi ; A.A. Abidi
Sponsor(s): VLSI Soc. of India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2007
Conference Location: Bangalore, India
Conference Date: 6 January 2007
Page(s): 135 - 140
ISBN (Paper): 0-7695-2762-0
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2007.42
Regular:

A software-defined radio receiver is designed from a low power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To... View More

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