IEEE - Institute of Electrical and Electronics Engineers, Inc. - Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits

2007 20th International Conference on VLSI Design

Author(s): Sanghoan Chang ; Gwan Choi
Sponsor(s): VLSI Soc. of India
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2007
Conference Location: Bangalore, India
Conference Date: 6 January 2007
Page(s): 109 - 114
ISBN (Paper): 0-7695-2762-0
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2007.88
Regular:

This paper presents a novel design approach for addressing the pressing problem of noise and signal integrity in high-speed circuits. The approach uses a combination of gate-level redundancy in... View More

Advertisement