IEEE - Institute of Electrical and Electronics Engineers, Inc. - On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence

APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Song Chen ; T. Yoshimura
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2006
Conference Location: Singapore, Singapore
Conference Date: 4 December 2006
Page(s): 1,867 - 1,870
ISBN (Paper): 1-4244-0387-1
DOI: 10.1109/APCCAS.2006.342203
Regular:

3D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3D IC floorplanning. It is... View More

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